TSMC announces 2nm process that brings 30% efficiency gain

Preparations for the 2nm process, which will carry the efficiency to much higher levels in chips, have come to the final stage. TSMC supports its processes with new technologies.
 TSMC announces 2nm process that brings 30% efficiency gain
READING NOW TSMC announces 2nm process that brings 30% efficiency gain

Taiwanese TSMC, the pioneer of the chip casting industry, is currently trying to stick to its roadmap, although there are some delays in the development of the 3nm process. The company’s 2nm process promises better performance.

What does the 2nm process bring?

Called TSMC N2 , the 2nm process uses a new technology called GAAFETs that turn the field around with gates. Channels made of nanolayer transistors are surrounded by gates on all four sides. Thus, power leaks are reduced, channels can be narrowed and expanded, and performance can be scaled. In addition, the power lines at the rear are also used to improve performance per watt.

TSMC will challenge its customers

added 1 day ago

While the TSMC N2 process performs 10-15 percent better than the N3E process at the same energy level, it can consume 25-30 percent less energy at the same performance level. It is stated that the chip density has increased by 1.1 times.

The N3E process actually came with slightly more improvements than the N5 process. The 2nm process does not bring improvements at the same rate, but the difference will be slightly wider in the next versions. The TSMC N2 process is planned to be implemented in 2025.

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