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Intel and TSMC are moving forward on next-generation CFET transistors

According to the latest information, Intel and TSMC will share advances in vertically stacked complementary field effect transistors (CFET) at the upcoming International Electron Devices Meeting (IEDM) conference. This technology has not yet...
 Intel and TSMC are moving forward on next-generation CFET transistors
READING NOW Intel and TSMC are moving forward on next-generation CFET transistors
According to the latest information, Intel and TSMC will share advances in vertically stacked complementary field effect transistors (CFET) at the upcoming International Electron Devices Meeting (IEDM) conference. Although this technology is still in its infancy, it is expected to replace the GAA (Gate-All-Around) solution in the next decade.

Development continues in CFET transistors

The CFET concept, which first emerged in 2018, involves placing n- and p-type transistors on top of each other. In context: N- and P-type transistors are key components used to control or amplify electrical signals between semiconductor devices. Although the first steps for CFETs have been taken by academic circles, companies such as Intel and TSMC have been actively working in this field for a while.

Intel has built a monolithic 3D CFET using a vertical structure that includes PowerVia backside power distribution. This new technology includes functional inverter test circuits with a 60nm gate pitch. TSMC, on the other hand, is discussing the applied CFET method with a 48nm gate pitch. This design places n-type nanosheet transistors on top of their p-type counterparts, providing a significant performance increase. It is stated that TSMC’s transistors have proven their durability and more than 90 percent passed the tests.

New generation transistor

CFETs are a significant change in transistor design, aiming to increase on-chip transistor density by allowing two transistors to fit into the space occupied by one transistor through vertical stacking. This design not only paves the way for improved area efficiency, but also facilitates improved design efficiency by supporting a more modern CMOS logic circuit layout.

Additionally, the inherent structure of CFETs can lead to reduced parasitic effects, offering potential increases in performance and power efficiency. Adaptive design capabilities, combined with innovations such as backside power distribution, could further streamline the manufacturing process, making CFETs a promising development in the field of transistor technology. The efforts of both Intel and TSMC demonstrate the importance of CFET technology in the semiconductor industry.

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