AMD released the Ryzen 9 7950X3D processor late last month. With this processor, the second generation 3D V-Cache technology entered our lives. While the tests put the Ryzen 9 7950X3D at the top in game performance and energy efficiency, AMD finally shared some technical details a while ago.AMD increases bandwidth by 25 percent on 2nd Gen 3D V-Cache
While maintaining the chiplet design in the Ryzen 7000X3D series, AMD announced that it uses 5nm processes for CCD (Core Chiplet Die), 6nm for IO die and 7nm for V-Cache. Therefore, AMD once again used 7nm manufacturing processes for V-Cache. However, despite this, the company has managed to preserve the amount of transistors while reducing the membrane area of V-Cache memories and has increased the bandwidth by 25 percent (2.5 TB / s). Therefore, we can say that there is a serious engineering success here. As AMD moves to the second generation 3D V-Cache, Intel still has not developed a competing technology. Therefore, this makes AMD stand out in both gaming and latency-sensitive business areas.
AMD’s first generation 3D V-Cache used 7nm L3 SRAM chips on top of the 7nm Zen 3 CCD (process die/cores) chip. While AMD adhered to 7nm SRAMs in the second generation, it started to produce the chip with the CCD at 5nm with Zen 4. Thus, a size mismatch arose.
AMD has managed to increase the density while reducing the die size
| DH | 2nd generation 3D V-Cache | 1st generation 3D V-Cache | Zen 4 CCD | Zen 3 CCD |
|---|---|---|---|---|
| Production process | 7nm | 7nm | 5nm | 7nm |
| Dimension | 36mm^2 | 41mm^2 | 66.3mm^2 | 80.7mm^2 |
| Transistor | ~4.7 Billions | 4.7 Billions | 6.57 Billions | 4.15 Billion |
| Transistor density (mm2) | ~130.6 Million | ~114.6 Million | ~99 Million | ~51.4 Million |
To address this size discrepancy, AMD downsized the 7nm SRAM die from 41mm2 in the previous generation to 36mm2. However, AMD has managed to increase the density significantly while keeping the 4.7 billion transistor count while shrinking the die. In addition, although AMD has practically reduced the size of the Zen 4 CCD, it has also managed to almost double the transistor density in the core die. You can compare the transistor, core density and areas from the table above.
Data and energy transfer to the stacked L3 SRAM chips used for 3D V-Cache is performed with silicon-based TSV interconnects. In the first generation design, both TSV types (energy and data) were housed in the L3 memory bay of the base chipset. However, due to the increased density in the 5nm process, AMD has shrunk the L3 cache on the base die further, and the 7nm L3 SRAM chips have been placed in a structure to overlap with the L2 caches, albeit scaled down.
This is why AMD had to replace the TSV connections on both the base die and the L3 SRAM chip. It seems that the firm has shrunk TSV connections in order to increase efficiency. However, as a result of these changes, AMD has consolidated their 3D V-Cache memory in a single CCD chip of the processor. Although efficiency and durability improvements have been made in the new generation, sensitivity to heat has not been eliminated. Therefore, one of the CCD chip of the new generation 3D processors works at lower frequency and voltage values.For example, Ryzen 9 7950X3D has two CCDs and one of them has 3D memories. The clock speed of the chip with 3D memories is 5.25 GHz in a single core, 4.85 GHz in multi-core, and the voltage is 1.152v. The clock speed of the other chip without 3D is 5.75 GHz and 5.3 GHz, respectively. The applied voltage for this chip is 1.384v.
As a result, AMD eliminated unnecessary or inefficient areas in the design and reduced the size of some components in order to combine Zen 4 with the second generation 3D V-Cache and increase performance even more compared to the previous generation. By increasing the capacity of the L3 cache to 96 MB in a single chip, AMD has also increased the bandwidth to 2.5 TB / s.
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